this datasheet contains new product information. anachip corp. re serves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev. 1.0 dec 16, 2004 1/10 peel? 22cv10a -7/-10/-15/-25 cmos programmable electric ally erasable logic device features high speed/low power - speeds ranging from 7ns to 25ns - power as low as 30ma at 25mhz electrically erasable technology - superior factory testing - reprogrammable in plastic package - reduces retrofit and development costs development/programmer support - third party software and programmers - anachip place development software general description the peel?22cv10a is a programmable electrically eras- able logic (peel?) device providing an attractive alterna- tive to ordinary plds. the peel?22cv10a offers the performance, flexibility, ease of design and production practicality needed by logic designers today. the peel?22cv10a is available in 24-pin dip, soic, tssop and 28-pin plcc packages (see figure 1), with speeds ranging from 7ns to 25ns and with power consumption as low as 30ma. ee-reprogrammability provides the conve- nience of instant reprogramming for development and a reusable production inventory, minimizing the impact of programming changes or errors. ee-reprogrammability architectural flexibility - 132 product term x 44 input and array - up to 22 inputs and 10 outputs - up to 12 configurations per macrocell - synchronous preset, asynchronous clear - independent output enables - 24-pin dip/soic/tssop and 28-pin plcc application versatility - replaces random logic - pin and jedec compatible with 22v10 - enhanced architecture fits more logic than ordinary plds also improves factory testability, thus ensuring the highest quality possible. the peel?22cv10a is jedec file com- patible with standard 22v10 plds. eight additional configu- rations per macrocell (a total of 12) are also available by using the ?+? software/programming option (i.e., 22cv10a+ & 22cv10a++). the additional macrocell configurations allow more logic to be put into every design. programming and development support for the peel?22cv10a are pro- vided by popular third-party programmers and develop- ment software. anachip also offers free place development software. figure 1. pin configuration figure 2. block diagram i/clk 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 i 11 gnd 12 24 vcc 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i dip tssop plcc *optional extra ground pin for -7/i-7 speed grade. soic 9 not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 2/10 not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 3/10 function description the peel?22cv10a implements logic functions as sum- of-products expressions in a programmable-and/ fixed-or logic array. user-defined functions are created by program- ming the connections of input signals into the array. user- configurable output structures in the form of i/o macrocells further increase logic flexibility. architecture overview the peel?22cv10a architecture is illustrated in the block diagram of figure 2. twelve dedicated inputs and 10 i/os provide up to 22 inputs and 10 outputs for creation of logic functions. at the core of the device is a programmable elec- trically-erasable and array which drives a fixed or array. with this structure, the peel?22cv10a can implement up to 10 sum-of-products logic expressions. associated with each of the 10 or functions is an i/o mac- rocell which can be independently programmed to one of 4 different configurations. the programmable macrocells allow each i/o to create sequential or combinatorial logic functions with either active-high or active-low polarity. and/or logic array the programmable and array of the peel?22cv10a (shown in figure 3) is formed by input lines intersecting product terms. the input lines and product terms are used as follows: 44 input lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 i/os 132 product terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14 and 16) used to form logical sums 10 output enable terms (one for each i/o) 1 global synchronous present term 1 global asynchronous clear term at each input-line/product-term intersection there is an eeprom memory cell which determines whether or not there is a logical connection at that intersection. each prod- uct term is essentially a 44-input and gate. a product term which is connected to both the true and complement of an input signal will always be false, and thus will not affect the or function that it drives. when all the connections on a product term are opened, a ?don?t care? state exists and that term will always be true. when programming the peel?22cv10a, the device programmer first performs a bulk erase to remove the previous pattern. the erase cycle opens every logical connection in the array. the device is then configured to perform the user-defined function by programming selected connections in the and array. (note that peel? device programmers automatically program the connections on unused product terms so that they will have no effect on the output function.) variable product term distribution the peel?22cv10a provides 120 product terms to drive the 10 or functions. these product terms are distributed among the outputs in groups of 8, 10, 12, 14 and 16 to form logical sums (see figure 3). this distribution allows opti- mum use of device re-sources. programmable i/o macrocell the output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configura- tion of the peel?22cv10a to the precise requirements of their designs. macrocell architecture each i/o macrocell, as shown in figure 4, consists of a d- type flip-flop and two signal-select multiplexers. the config- uration of each macrocell is determined by the two eeprom bits controlling these multiplexers (refer to table 1). these bits determine output polarity and output type (registered or non-registered). equivalent circuits for the four macro-cell configurations are illustrated in figure 5. output type the signal from the or array can be fed directly to the out- put pin (combinatorial function) or latched in the d-type flip- flop (registered function). the d-type flip-flop latches data on the rising edge of the clock and is controlled by the glo- bal preset and clear terms. when the synchronous preset term is satisfied, the q output of the register will be set high at the next rising edge of the clock input. satisfying the asynchronous clear term will set q low, regardless of the clock state. if both terms are satisfied simultaneously, the clear will override the preset. output polarity each macrocell can be configured to implement active-high or active-low logic. programmable polarity eliminates the need for external inverters. output enable the output of each i/o macrocell can be enabled or dis- abled under the control of its associated programmable output enable product term. when the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the i/o pin. otherwise, the output buffer is driven into the high-impedance state. under the control of the output enable term, the i/o pin can function as a dedicated input, a dedicated output, or a bi- directional i/o. opening every connection on the output not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 4/10 enable term will permanently enable the output buffer and yield a dedicated output. conversely, if every connection is intact, the enable term will always be logically false and the i/o will function as a dedicated input. input/feedback select when configuring an i/o macrocell to implement a regis- tered function (configurations 1 and 2 in figure 5), the q output of the flip-flop drives the feedback term. when con- figuring an i/o macrocell to implement a combinatorial function (configurations 3 and 4 in figure 5), the feedback signal is taken from the i/o pin. in this case, the pin can be used as a dedicated input or a bi-directional i/o. (refer also to table 1.) additional macro cell configurations besides the standard four-configuration macrocell shown in figure 5, each peel?22cv10a provides an additional eight configurations that can be used to increase design flexibility. the configurations are the same as provided by the peel?18cv8 and peel?22cv10az. however, to maintain jedec file compatibility with standard 22v10 plds the additional configurations can only be utilized by specifying the peel?22cv10a+ and peel22cv10a++ for logic assembly and programming. to reference these additional configurations please refer to the specifications at the end of this data sheet. design security the peel?22cv10a provides a special eeprom secu- rity bit that prevents unauthorized reading or copying of designs programmed into the device. the security bit is set by the pld programmer, either at the conclusion of the pro- gramming cycle or as a separate step after the device has been programmed. once the security bit is set, it is impos- sible to verify (read) or program the peel? until the entire device has first been erased with the bulk-erase function. signature word the signature word feature allows a 24-bit code to be pro- grammed into the peel?22cv10a if the peel?22cv10a+ software option is used. also, the sig- nature word feature allows a 64-bit code to be programmed into the peel?22cv10a if the peel?22cv10a++ soft- ware option is used. the code can be read back even after the security bit has been set. the signature word can be used to identify the pattern programmed into the device or to record the design revision, etc. figure 4. block diagram of the peel? 22cv10a i/o macrocell. not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 5/10 figure 5. four configurations of the peel?22cv10a i/o macrocell table 1. peel? 22cv10a macrocell configuration bits configuration # a b input/feedback select output select 1 0 0 register feedback register active low 2 1 0 active high 3 0 1 bi-directional i/o combinatorial active low 4 1 1 active high not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 6/10 additional macrocell configurations besides the standard four-configuration macrocells, each peel?22cv10a provides an additional eight configura- tions (twelve total) that can be used to increase design flex- ibility (see figure 6 and ta b le 2 ) . fo r logic assembly of all twelve configurations, specify peel?22cv10a+ and peel22cv10a++. figure 6. twelve configurations of the peel?22cv10a+ and peel22cv10a++ i/o macrocell table 2. peel? 22cv10a+ & a++ macrocell configuration bits configuration # a b c d input/feedback select output select 1 1 1 1 1 active low 2 0 1 1 1 register active high 3 1 0 1 1 active low 4 0 0 1 1 bi-directional i/o combinatorial active high 5 1 1 1 0 active low 6 0 1 1 0 register active high 7 1 0 1 0 active low 8 0 0 1 0 combinatorial feedback combinatorial active high 9 1 1 0 0 active low 10 1 0 0 0 register active high 11 1 0 0 0 active low 12 0 0 0 0 register feedback combinatorial active high not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 7/10 table 6. absolute maximum ratings this device has been designed and tested for the recommended operating conditions. i m p roper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may cause per- manent damage. symbol parameter conditions ratings unit v cc supply voltage relative to ground -0.5 to +7.0 v v i , v o voltage applied to any pin 2 relative to ground 1 -0.5 to vcc+0.6 v i o output current per pin (i ol , i oh ) 25 ma t st storage temperature -65 to +150 o c t lt lead temperature soldering 10 second +300 o c table 7. operating ranges symbol parameter conditions min max unit commercial 4.75 5.25 v cc supply voltage industrial 4.5 5.5 v commercial 0 +70 t a ambient temperature industrial -40 +85 o c t r clock rise time see note 3 20 ns t f clock fall time see note 3 20 ns t rvcc v cc rise time see note 3 250 ms table 8. d.c. electrical characteristics over the recommended operating conditions symbol parameter conditions min max unit v oh output high voltage v cc =min, i oh =-4.0ma 2.4 v v ohc output high voltage-cmos 13 v cc =min, i oh =-10a v cc -0.3 v v ol output low voltage-ttl v cc =min, i ol =-16ma 0.5 v v olc output low voltage-cmos 13 v cc =min, i oh =-10a 0.15 v v ih input high level 2.0 v cc +0.3 v v il input low level -0.3 0.8 v i il input leakage current v cc =max, v in =gnd v in ? v cc 10 a i oz output leakage current i/o=high-z, gnd v o v cc 10 a -7/i-7 140/155 10/i-10 135/145 -15/i-15 135/145 i cc 10 v cc current (see cr-1 for typical i cc ) v in =0v or 3v f=25mhz all outputs diabled 4 -25/i-25 67/75 ma c in 7 input capacitance 6 pf c out 7 output capacitance t a =25 o c, v cc =5.0v @f=1mhz 12 pf not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 8/10 table 9. a.c. electrical characteristics over the operating range 8,11 -1/i-7 -10/i-10 -15/i-15 -25/i-25 symbol parameter min max min max min max min max unit t pd input 5 to non-registered output 7.5 10 15 25 ns t oe input 5 to output enable 6 7.5 10 15 25 ns t od input 5 to output disable 6 7.5 10 15 25 ns t co1 clock to output 5.5 6 8 15 ns t co2 clock to comb. output delay via internal registered feedback 10 12 17 35 ns t cf clock to feedback 3.5 4 5 9 ns t sc input 5 or feedback setup to clock 3 5 8 15 ns t hc input 5 hold after clock 0 0 0 0 ns t cl , t ch clock low time, click high time 8 3 4 6 13 ns t cp min clock period ext(t sc +t co1 ) 8.5 11 18 30 ns f max1 internal feedback (1t sc +t cf ) 12 142 111 76.9 41.6 mhz f max2 external feedback (1/t cp ) 12 117 909 62.5 33.3 mhz f max3 no feedback (1/t cl +t ch ) 12 166 125 83.3 38.4 mhz t aw asynchronous reset pulse width 7.5 10 15 25 ns t ap input 5 to asynchronous reset 7.5 10 15 25 ns t ar asynch. reset recovery time 7.5 10 15 25 ns t reset power-on reset time for registers in clear state 5 5 5 5 ns switching waveforms inputs, i/o, registered feedback, synchronous preset clock notes asynchronous reset registered outputs combinatorial outputs 8. test conditions assume: signal transition times of 3ns or less from the 1. minimum dc input is -0.5v, however inputs may undershoot to -2.0v for periods less than 20ns. 2. v i and v o are not specified for program/verify operation. 3. test points for clock and v cc in t r , t f are referenced at 10% and 90% levels. 4. i/o pins are 0v and 3v. 5. ?input? refers to an input pin signal. 6. t oe is measured from input transition to v ref 0.1v, t od is measured from input transition to v oh -0.1v or v ol +0.1v; v ref =v l see test loads in section 5 of the data book. 7. capacitances are tested on a sample basis. 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 9. te s t one output at a time for a duration of less than 1sec. 10. icc for a typical application: this parameter is tested with the device programmed as an 8-bit counter. 11. peel? device test loads are specified in section 6 of this data book. 12. parameters are not 100% tested. specifications are based on initial characterization and are tested after any design or process modifica- tion which may affect operational frequency. 13. available only for 22cv10a -15/i-15/-25/i-25 grades. not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 9/10 table 6. ordering information part number speed temperature package peel22cv10ap-7 (l) c 7.5ns p24 peel22cv10api-7 (l) i peel 22cv10aj-7 (l) c 7.5ns j28 peel 22cv10aji-7 (l) i peel 22cv10as-7 (l) c 7.5ns s24 peel 22cv10asi-7 (l) i peel 22cv10at-7 (l) c 7.5ns t24 peel 22cv10ati-7 (l) i peel 22cv10ap-10 (l) c 10ns p24 peel 22cv10api-10 (l) i peel 22cv10aj-10 (l) c 10ns j28 peel 22cv10aji-10 (l) i peel 22cv10as-10 (l) c 10ns s24 peel 22cv10asi-10 (l) i peel 22cv10at-10 (l) c 10ns t24 peel 22cv10ati-10 (l) i peel 22cv10ap-15 (l) c 15ns p24 peel 22cv10api-15 (l) i peel 22cv10aj-15 (l) c 15ns j28 peel 22cv10aji-15 (l) i peel 22cv10as-15 (l) c 15ns s24 peel 22cv10asi-15 (l) i peel 22cv10at-15 (l) c 15ns t24 peel 22cv10ati-15 (l) i peel 22cv10ap-25 (l) c 25ns p24 peel 22cv10api-25 (l) i peel 22cv10at-25 (l) c 25ns t24 peel 22cv10ati-25 (l) i peel 22cv10aj-25 (l) c 25ns j28 peel 22cv10aji-25 (l) i peel 22cv10as-25 (l) c 25ns s24 peel 22cv10asi-25 (l) i not recommended for new designs - contact factory for availability
anachip corp. www.anachip.com.tw rev. 1.0 dec 16, 2004 10/10 part number peel tm 22cv10a pi-25x package p = plastic 300 mil dip s = soic temperature range andowe options (blank) = commercial 0 to 70 o c speed lead free blank : normal l : lead free package j = plastic (j) leaded chip carrier (plcc) suffix device t = tssop i = industrial -40 to +85 o c -7 = 7.5ns tpd -10 = 10ns tpd -15 = 15ns tpd -25 = 25ns tpd anachip corp. head office , anachip usa 2f, no. 24-2, industry e. rd. iv, sci ence-based 780 montague expressway, #201 industrial park, hsinchu, 300, taiwan san jose, ca 95131 tel: +886-3-5678234 tel: (408) 321-9600 fax: +886-3-5678368 fax: (408) 321-9696 email: sales_usa@anachip.com website: http://www.anachip.com ?2004 anachip corp. anachip reserves the right to make changes in specifications at any time and wit hout notice. the information furnished by anachip in this publication is believed to be accurate and reliabl e. however, there is no responsibility assumed by anachip for its use nor for any infringements of patents or other rights of third parties resultin g from its use. no license is granted und er any patents or patent rights of anachip. a nachip?s products are not authorized for us e as critical components in life support devices or systems. marks bearing ? or ? are registered trademar ks and trademarks of anachip corp. not recommended for new designs - contact factory for availability
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